Accurate timing, set by one or more clock signals, is crucial for proper operation of any digital system. Various techniques exist for generating and distributing clock signals over an integrated circuit chip. For example, a primary clock may be generated (or received from an external source through an input/output (I/O) pin) and then routed to various components within the chip that use the clock signal. For example, in a microprocessor, a system clock signal must be distributed to a large number of clock pins, distributed in different parts of the microprocessor.
Clock skew is a relative difference in time that the clock signal takes to reach different parts of the integrated circuit. Ideally, clock signals should have no skew, and the clock signals should reach various components at the same time. However, as the components may be distributed in different areas of the chip, clock signals reaching the components may experience different propagation delays (based on the location of the components on the chip and the distance the clock signal may have to travel to reach a component), resulting in a systematic clock skew. That is, a systematic clock skew may arise because of unequal distances covered by a clock signal to reach various components.
Clock skew may also depend on various other factors, such as process variations, voltage drop (IR (current times resistance) drop) within the chip, supply voltage fluctuation, temperature gradient within different areas in the chip, etc, creating random clock skew.
An H-tree is commonly used in very large scale integrated (VLSI) circuit design as a clock distribution network for routing timing signals to all parts of a chip, aiming to equalize the distances covered by a clock signal to reach various components within an integrated circuit device, thereby reducing or eliminating systematic clock skew. In an H-tree layout, a set of wires (optionally driven by appropriate signal drivers) for carrying the clock signal is laid out in a tree-like structure. The shape of the layout is such that each division or split of the clocking signal wire leads into two branches of identical length. The result is that each branch of the clocking signal path has the substantially similar impedance characteristics and propagation delay, leading to a balanced clock signal.
FIG. 1 illustrates an exemplary H-tree 10. The H-tree may be used to deliver a clock signal CLK to a clock grid (not illustrated) within an integrated circuit chip (not illustrated). The arrows shown at the end of some of the branches of the H-tree 10 are signal drivers, positioned at different nodes of the H-tree. Note that in FIG. 1, only a few signal drivers of the H-tree 10 have been illustrated for the sake of clarity. As will be readily appreciated by those skilled in the art, although not illustrated, all branch ends (i.e., all the nodes) of the H-tree may have a signal driver. Also note that some of the branches of the H-tree have been magnified in the figure for illustrative purposes only.
The H-tree 10 of FIG. 1 includes a plurality of stages, each stage including respective branches and signal drivers. For example, a 1st stage of the H-tree includes signal driver A′1 that drives the signal CLK to the next stage. B′1 and B′2 form the signal drivers of the second stage, and C′1, C′2, C′3, and C′4 form the signal drivers of the 3rd stage. As seen from FIG. 1, the H-tree 10 has 9 stages (A, . . . , I). As will be readily understood, with an increase in the stage, the number of signal drivers may double. Hence, for the sake of clarity, from 4th stage onwards, only a few of the signal drivers in each stage are illustrated in the figure. For example, for the last stage (i.e., the 9th stage), only the drivers I′1, I′2, I′20, 1′21, and I′30 are illustrated. The last stage drivers (I′1, I′2, . . . ) of the H-tree 10 may drive a clock network, from which various components within the chip may tap the clock signal.
FIG. 2 illustrates an exemplary grid-shaped clock network 15 that may be provided with clock signals, at various points of the network 15, through the last stage csignal drivers of the H-tree 10 of FIG. 1. For example, the last stage signal drivers I′1, I′2, . . . , I′20, I′21, . . . , I′30, . . . of the H-tree 10 may provide the clock signal CLK at various points of the network 15. The clock network 15 may be included in an integrated circuit chip and may comprise conductive elements or metal strips carrying the clock signal to most parts of the chip. Various components in the chip (not illustrated) may tap the clock signal from different points of the clock network 15, based on the location of a component.
Referring again to FIG. 1, the branches of the H-tree may be symmetrical, as is well known in the art. That is, for each stage, all branches may have substantially equal length. For example, the length of the branch between A′1 and B′1 may be substantially similar to the length of the branch between A′1 and B′2. The same principle applies to the other branches in subsequent stages as well. This balanced nature of the branches and nodes of an H-tree ensure that the length (and the number of nodes) traveled by the CLK signal to reach each of the signal drivers (e.g., I′1, I′2, I′20, I′21, . . . , I′30, . . . ) of the last stage are substantially similar. Thus, the H-tree eliminates any systematic skew of the clock, because the distances covered by the clock signal to reach various areas of the chip are substantially equal.
Additionally, although it is assumed that all nodes of an H-tree include signal drivers, in various embodiments, this may not be necessary, and an H-tree may be easily envisioned with fewer signal drivers. For example, all nodes of a particular stage of an H-tree may not have any signal driver. In various embodiments, if a signal driver of a node in a given stage is added or deleted, similar action may be taken for all other nodes of that stage in order to keep the H-tree balanced. Furthermore, although the signal drivers are illustrated to be positioned at the nodes of the tree, it may not be necessary to do so. For example, a signal driver may be positioned at the middle of a branch, instead of being positioned at a node.
It should be noted that the H-tree 10 of FIG. 1 is exemplary in nature. Various other shapes (having a different number of stages, for example) of an H-tree are also possible. For example, FIG. 3 illustrates various exemplary configurations of H-trees, each with different number of stages.
FIG. 4 illustrates an exemplary voltage drop (sometimes referred to as an IR drop in the art (i.e., current multiplied by resistance)) gradient plot over an area of an exemplary integrated circuit chip. The figure illustrates the spatial nature of the IR drop, i.e., how the IR drop changes over the area of the chip. As is well known in the art and illustrated in FIG. 4, IR drop plots may exhibit approximate ring (or square) like shapes, with higher IR drops at the center of the core and the IR drop lowers as one moves towards the periphery of the chip. For example, referring to FIG. 4, the outer periphery of the chip may experience less IR drop (10 mV) compared to the inner core, which may experience a higher IR drop (50 mV). However, it should be apparent that the numerical values of the IR drop are purely exemplary in nature, and that IR drops may depend on various other factors, such as the supply voltage, the type and form factor of the chip, etc.
Similar to the IR drop, temperature in an integrated circuit chip may also exhibit spatial properties. For example, temperature of a point in the chip may be based on various factors, including but not limited to a distance of the point from the center of the chip. Although not illustrated, die temperature plots may also exhibit approximate ring (or square) like shapes, with hotter rings starting at the center of the core and cooler rings being located towards the periphery, as is well known to those skilled in the art.
The IR drop illustrated in FIG. 4 and the uneven temperature gradient over the area of a chip may affect the working of the H-tree 10 of FIG. 1. For example, the temperature and the IR drop experienced by a signal driver of the H-tree may depend of the distance of the driver from the center (marked by the 1st stage signal driver A′1) of the H-tree (note that it is assumed that the center of the chip and the center of the H-tree 10 are identical, although this may not necessarily be the case). For example, all four (C′1, C′2, C′3, and C′4) signal drivers of the 3rd stage of the H-tree 10 are equidistant from the center of the tree and hence, experience substantially similar temperature gradient and IR drops. However, branches and signal drivers of subsequent stages may have different distances from the center of the H-tree. For example, signal drivers F′1 and F′20 are both stage 6th stage drivers. However, these two drivers have unequal physical distance from the center (at A′1) of the H-tree. That is, although a clock signal may traverse a substantially similar length to reach the drivers F′1 and F′20, the driver F′20 is physically near the center of the H-tree compared to the driver F′1. Similarly, signal drivers I′1 and I′20 (both 9th stage drivers) are located at an unequal distance from the center of the chip.
Such unequal distances result in the signal drivers (and corresponding branches) of any given stage experiencing different IR drops and different temperature gradients. For example, signal driver F′20 (located near the center of the chip) may experience a higher IR drop compared to signal driver F′1 (located near the periphery of the chip, see FIGS. 1 and 4). Also, for the same reason, signal driver F′20 may be in a higher temperature region compared to signal driver F′1.
That is, different signal drivers (and corresponding branches) of the same stage of the H-tree 10 may experience different levels of IR drop and different temperatures. This may introduce different amounts of random skews in the signal drivers and branches of the same stage. Consequently, the clock signal reaching different signal drivers of the last stage of the H-tree may experience different propagation delays, resulting in a skew in the clock signal.